1. Field of the Invention
The invention relates to a method of fabricating a shallow trench isolation (STI), and more particularly to a method of preventing the formation of field oxide recess on the surface of an STI.
2. Description of the Related Art
In a complete circuit, for example, an integrated circuit (IC), thousands of metal-oxide-semiconductors (MOS) transistors are formed. To prevent short circuit between adjacent MOS transistors, an insulation layer, for example, a field oxide layer (FOX), or an STI for isolation is formed to defined an active region.
STI is a common conventional structure of isolating devices. A nitride layer is formed on the substrate as an etching mask. Using anisotropic etching, a trench is formed. The trench is then filled with oxide until its surface level is about the same as the substrate surface. The STI fabricated by the above conventional method has a field oxide recess.
Referring to FIG. 1A to FIG. 1G, a conventional method of fabricating an STI is shown. In FIG. 1A, a pad oxide layer 12 is formed on a substrate 10. Using chemical vapor deposition (CVD), a silicon nitride layer 14 is formed on the pad oxide layer 12. A photo-resist layer 18 is formed and patterned on the silicon nitride layer 14.
Using the photo-resist layer 18 as a mask, the silicon nitride layer 14, the pad oxide layer 12, and the substrate 10 are etched to form a trench 16 which penetrates through a part of the substrate 10.
In FIG. 1C, the photo-resist layer 18 is removed. The trench 16 is filled with an oxide layer 26, for example, a silicon oxide layer formed by atmosphere pressure CVD (APCVD) with tetra-ethyl-ortho-silicate (TEOS) as a gas source. In the case of a TEOS base oxide layer, a process of densification is performed after deposition at about 1000.degree. C. for 10 min to 30 min.
In FIG. 1D, using chemical-mechanical polishing (CMP), the TEOS base silicon oxide layer 26 is removed with the silicon nitride layer 14a as an etch stop layer. An oxide plug 36 is formed within the trench 16. Since the oxide plug 36 is softer than the silicon nitride layer 14, during CMP, a recess (not shown) is formed in the junction between the oxide plug 36 and the silicon nitride layer 14.
In FIG. 1E, the silicon nitride layer 14 is removed to expose the pad oxide layer 12. While removing the silicon nitride layer 14, normally, the rim of the oxide plug 36 is removed, so that in the subsequent process for etching the oxide plug 36 and the pad oxide layer 12, a recess is easily formed.
In FIG. 1F, using hydrogen fluoride (HF) as an etchant, the pad oxide layer 12 and the oxide plug 36 are wet etched until the oxide plug 36 and the surface of the substrate 10 are at a same level. The edge of the oxide plug 36, that is, the junction between the oxide plug 36 and the substrate 10, is over etched to cause a field oxide recess 46a. The formation of the field oxide recess 46a affect the quality of device, for example, the threshold voltage is reduced, the abnormal critical current and leakage current occur.
In FIG. 1G, a gate oxide layer 22 is formed by thermal oxidation. The MOS transistor is formed by the conventional method.
In the conventional method, the formation of the field oxide recess causes an accumulation of charges. The electric field is increased, the threshold voltage for turning on operation is increased, and more than once, an abnormal subthreshold current is produced. This is the so called "kink effect". In addition, a corner parasitic MOS transistor is formed, so that device leakage current occurs. The reduced threshold voltage, the abnormal subthreshold current, and the leakage degrade the quality of device and reduce the yield of production.